Every chip designer has been there. Your simulation crashes at cycle 47,392,881. The waveform viewer takes four minutes to launch—assuming the license server cooperates at all. You're staring at thousands of signal traces, hunting for a glitch that could push your tapeout back by months. And here's the part that really stings: you'll spend 70% of your project timeline doing exactly this.
The industry's dirty secret is getting dirtier. First-silicon success rates for ASIC and SoC projects have collapsed to 14%, according to Siemens EDA's functional verification study published in September 2025—the lowest mark in more than two decades. Verification still devours 60 to 70% of engineering effort, a stubborn ratio that hasn't improved despite successive waves of tooling upgrades. The response? A three-way race among incumbents to rebuild the entire chip design stack with AI agents, starting with the debugging workflow that burns the most time and money.
That's the arena a two-person startup called Hardware Intelligence walked into last summer. The YC-backed company launched Wave, a terminal-native waveform debugger with a built-in verification agent, targeting what the founders call "the $20 billion industry whose debuggers suck and won't open until an ancient license server gives it permission." It's a blunt pitch for what may be the semiconductor industry's most consequential infrastructure bet since the migration to cloud-based simulation.
Whether it works is another matter.
When Your Tools Are Older Than Your Engineers
The Electronic System Design market pulled in $5.5 billion during the final quarter of 2025, per the ESD Alliance's reporting from April 2026. That figure—covering EDA tools, IP, and services—represents a sector where three names dominate. SemiAnalysis estimated in mid-2026 that Synopsys commanded roughly $8 billion in annual revenue (including Ansys, which it acquired in July 2025), Cadence about $5.3 billion, and Siemens EDA between $2.2 billion and $2.5 billion for 2025. The Big Three control approximately $16 billion of the market.
Those billions fund the tools that turn hardware descriptions into manufacturable silicon. But increasingly, those tools struggle to keep up with chip complexity. Chiplets, 3D-IC architectures, software-defined hardware—all of it converges into verification nightmares that legacy debuggers weren't built to handle. Harry Foster of Siemens EDA observed in analysis from late 2024 that system companies entering silicon face particularly steep verification maturity curves, calling for "new verification productivity paradigms" to reverse the first-silicon success decline.
The incumbents have noticed. At the Design Automation Conference last July, all three announced expanded AI initiatives. Synopsys touted its 100th production tapeout using DSO.ai, its reinforcement-learning-driven design optimizer, highlighting customer results showing productivity gains exceeding 3x alongside power reductions up to 15%. Cadence positioned Cerebrus AI Studio for multi-block SoC flows, pointing to Samsung metrics: 8 to 11% PPA (power, performance, area) improvements on subsystems and 4x overall productivity gains. Siemens declared that "agentic AI is the natural path forward" for orchestrating multi-domain verification across chiplets and 3D-ICs.
Whether those productivity claims hold up under independent scrutiny remains an open question. But the messaging is clear: everyone's racing toward agents.
Why Now? Three Converging Pressures
The technical challenge is outrunning human capacity. Modern SoCs pack billions of transistors across multiple chiplets, each with its own power domain, clock domain, and interface protocol. Siemens' 2024 study documented how verification complexity from these architectures has grown faster than team sizes or budgets. Debug sessions that once took hours now stretch into days. Waveform files routinely exceed terabytes.
The tooling itself feels ancient by software standards. The dominant commercial debuggers—Synopsys Verdi, Cadence SimVision, Siemens Questa Visualizer—are mature, GUI-heavy applications often gated by license servers. They're powerful, certainly, but they weren't designed for the terminal-centric, SSH-friendly workflows many verification engineers now prefer. Nor were they built for agentic AI integration. Open-source alternatives like GTKWave fill some gaps but lack enterprise features and AI hooks.
Then there's the geopolitical piece, which has intensified sharply. The U.S. CHIPS Act allocated billions to domestic fab capacity—Intel was announced to potentially receive up to $8.5 billion, TSMC up to $6.6 billion, Samsung up to $6.4 billion in announcements made during 2024. The EU launched its own Chips Act, investing €700 million into a NanoIC pilot line. India expanded its Design Linked Incentive scheme. All of this new capacity needs designers and verification engineers who can work faster than their predecessors.
Export controls complicate matters further. BIS rules initiated in 2022 and updated through recent years now restrict EDA tool access for advanced nodes. An enforcement action against Cadence in early 2026 for alleged illegal exports signaled a tightening climate. Even license renewals can fall under scrutiny.
These pressures create an opening for AI. But not the chatbot kind. The agent kind, capable of re-running simulations, proposing fixes, and triaging regressions autonomously.
The Insurgent's Play
Hardware Intelligence's approach is almost aggressively minimal. Wave reads VCD and FST waveform formats currently, with FSDB support offered on a partnership basis. It runs entirely on-premises with the user's own model key, fits into SSH and tmux workflows, offers Vim bindings, and includes a waveform diff feature to compare failing and fixed simulations side by side. The pitch is speed and control: no waiting for a license server, no uploading proprietary IP to someone else's cloud, an agent that shows "evidence-pinned answers" directly in the terminal viewer.
Founders Athreya Anand and Rishov Sarkar are betting that verification engineers will trade polish for pragmatism. Anand previously led agentic workflow tools at Google, with earlier stints at AWS Inferentia and Tesla. Sarkar, a Georgia Tech ECE PhD, developed simulators for AMD's AI Engine and worked on LLVM-based compilation at Siemens EDA before YC. Their launch framed Wave as a "fight" with incumbents, but it's also a bet on where the market is headed: toward agent-native workflows that don't require leaving the command line.
The Big Three, meanwhile, are embedding AI across entire flows. Synopsys's DSO.ai has now taped out more than 100 production designs, spanning power optimization, area reduction, and timing closure—design tasks where reinforcement learning can explore parameter spaces faster than human engineers. Synopsys also partnered with Microsoft in late 2023 to build Synopsys.ai Copilot, a GenAI assistant for chip design, with subsequent rollouts expanding into verification and debug.
Cadence's Cerebrus AI Studio pushes further into agentic territory. The platform orchestrates multiple AI agents across design blocks and user teams, tackling multi-block SoC optimization. Samsung Semiconductor India Research reported 8 to 11% PPA improvements on subsystems using Cerebrus, while Samsung Austin R&D Center documented 4x productivity gains (both metrics published in mid-2025). Renesas announced its adoption of Cerebrus early this year. Cadence also unveiled its Millennium M2000 supercomputer last year, built on NVIDIA Blackwell systems to accelerate AI-driven simulation and computational workloads.
Siemens EDA announced at last year's DAC what it calls "self-verifying AI workflows," spanning Catapult high-level synthesis, Questa and Veloce simulation, Solido analog verification, Aprisa place-and-route, Calibre physical verification, and Tessent test. The vision, per Abhi Kolpekwar, SVP and GM of Digital Verification, is agentic AI that orchestrates verification across chiplet and 3D-IC boundaries. It's a clear acknowledgment that verification can no longer be a single-tool, single-domain problem.
The startup landscape is heating up, too. Ricursive Intelligence, founded by AlphaChip leads Anna Goldie and Azalia Mirhoseini, launched in late 2025 with a $35 million seed round at a $750 million valuation. The company is pursuing an "end-to-end AI model for chip design," though specifics remain sparse. SigmanticAI, another YC alum, offers LLM-powered Verilog and RTL generation with compiler-in-the-loop refinement and an air-gapped deployment option. Zero ASIC launched its Tardigrade synthesis engine last summer, positioning it as built for "the AI-driven design era."
Academic work is accelerating. A National Science Foundation AI-EDA workshop report from early 2026 synthesized community needs: standard datasets and benchmarks, verification of AI outputs, robust optimization under uncertainty, and security. Researchers have published multi-agent verification automation frameworks and coding agents for OpenROAD that demonstrated up to 10% effective clock period reduction and nearly 6% wirelength reduction. VeriPilot, an HDL agent framework, appeared in mid-2026. The gap between research and production is narrowing.
The Narrow Path Ahead
The immediate future feels certain: every major EDA vendor will ship agents. The question is what kind, and for whom.
Synopsys, Cadence, and Siemens have customer relationships, process certifications, and decades of domain knowledge. Their agents will likely excel at tasks where the tool feedback loop is tight—PPA optimization, regression triage, constraint debugging. But their pricing models and licensing infrastructure were built for a different era. An on-premises agent that requires a floating license and a six-figure annual contract is a tough sell to startups or teams experimenting with AI-assisted workflows.
This creates room for challengers like Hardware Intelligence, though the path is narrow. To displace an incumbent debugger, a new tool needs to be not just faster or cheaper—it needs to enable a workflow the old tool can't. Wave's bet on terminal-native, agent-driven debug could resonate with verification engineers who already live in tmux and Vim, especially at companies wary of cloud-based LLMs for IP protection reasons. Multiple enterprise AI infrastructure surveys from the past year highlighted sovereignty and security concerns driving on-premises deployments, a trend Wave explicitly targets with its "all local—your machines, your model key, not our cloud" positioning.
There are challenges, naturally. Export controls now restrict EDA tool access to certain destinations, and even license renewals can fall under regulatory scrutiny. Any new EDA tool will need to navigate these regulations. Data and benchmark availability is another bottleneck—the NSF report calls for standard datasets and tasks, but those don't yet exist at industry scale. And buyers will expect measurable deltas. Cadence and Synopsys customers have published productivity multiples and PPA improvements; Hardware Intelligence will need similar proof points.
The broader trend points toward agent orchestration across the entire design flow. NVIDIA and TSMC announced last year that TSMC is using NVIDIA's cuLitho for GPU-accelerated computational lithography in production fabs, while also deploying AI for process control. This compresses design-manufacture iteration cycles, which should incentivize tighter co-optimization between EDA tools and fab operations. Siemens's "self-verifying AI workflows" across multiple tools point in a similar direction: agents that don't just optimize a single design step but orchestrate verification across chiplets, analog blocks, and test insertion.
Verification and debug will remain the largest time sink, so tools that shorten "find and fix" cycles—or make agent actions auditable and evidence-backed—will see early adoption. Pilots are likely at companies already running on-premises LLMs for code generation or security analysis, particularly those with air-gapped environments. The first wins will probably be niche: startups that don't have Verdi seats, teams debugging FPGA prototypes in terminals, or verification groups at system companies new to silicon who need to compress learning curves.
What to Watch
Founders and CTOs should track a few signals. How quickly the Big Three move their agents from optimization (where they're strong today) into root-cause analysis and iterative debug (where humans still dominate). Whether industry benchmarks and datasets materialize in the next 12 to 18 months, enabling apples-to-apples comparisons. And whether on-premises, agent-native tools can carve out a wedge before the incumbents adapt.
The verification crisis is real. First-silicon success at 14% is unsustainable. Seventy percent of engineering effort spent on verification is a tax the industry can't afford as chip complexity doubles every generation. AI agents won't fix all of it—there's still debate around the generalizability of tools like AlphaChip, and early productivity claims need independent validation. But the trajectory is set.
The debuggers that powered the last two decades of chip design are being rebuilt. The companies that get agent workflows right will define the next twenty years. Whether that's a two-person YC startup or a multi-billion-dollar incumbent with decades of installed base remains to be seen. But the race is on, the stakes are enormous, and the clock—as any chip designer will tell you—is always ticking.
